1. Field of the Invention
The present invention generally relates to a method of programming and erasing flash memories. More specifically, the present invention provides a method of programming and erasing triple-poly split-gate flash memories.
2. Description of the Related Art
Since a flash memory device can be programmed and erased by electronic operations, such as applying different voltages, it has become a widely used memory module.
There are several popular flash memory cell structures. The first flash memory cell is the so-called stacked gate double-poly flash cell, abbreviated by ETOX, as depicted in FIG. 1 (Prior Art). In FIG. 1, numeral 1 represents a substrate layer or substrate region. Numeral 3 represents a drain region and numeral 5 represents a source region. The gate structure is constructed by two stacked polysilicon layers, including an embedded floating gate 10 and an exposed control gate 12 which can be directly applied to voltage signals. Similar to metal-oxide-silicon (MOS) transistors, such a flash memory cell also has an oxide layer 7 between the floating gate 10 and the channel 8 linking the drain region 3 and the source region 5. A dielectric layer 9 is sandwiched between the floating gate 10 and the control gate 12. The dielectric layer 9 can be used to couple the voltage of the control gate 12 to the floating gate 10 for generating a strong electric field to trap electrons. In addition, the dielectric layer 9 also serves as an isolation barrier to encapsulate the electrons trapped in the floating gate 10. Numeral 4 represents spacers around the gate structure.
The programming and erasing procedures of such a stacked gate double-poly flash memory cell are described as follows. Programming or storing data is achieved by channel hot electrons. In detail, a strong electric field, which is induced by the potential difference between the coupled positive voltage of the floating gate 10 and the voltage of the channel 8, can provide electrons with enough kinetic energy to penetrate the oxide layer 7. Therefore, these hot electrons are trapped in the floating gate 10. The presence or absence of the electrons trapped in the floating gate 10 affects the conducting state of channel 8 beneath the floating gate. Therefore, each memory cell can be programmed to store "1" or store "0" according to the absence or presence of the trapped charges in the floating gate 10. Erasing or deleting data is achieved by releasing the trapped charges in the floating gate 10 by Flowler-Nordheim (F-N) tunneling effect. A huge negative voltage is directly applied to the control gate 12 and coupled to the floating gate 10 for driving the trapped electrons in the floating gate 10 to tunnel the oxide layer 7 and to be released through the channel 8 beneath the floating gate or through the source region 5.
However, the conventional stacked gate double-poly flash memory still suffers some drawbacks. For example, the operation of the stacked gate double-poly flash memory has the phenomenon of over-erasing, wherein the threshold voltage of the transistor in the memory cell becomes negative if the erasing operation is overdone. Such a situation may cause the current leakage of the memory column bias circuitry. In addition, the programming current of the programming operation, which is about 0.5.about.1 mA for each memory cell, is quiet large.
A new cell structure, called the double-poly split-gate memory cell, has been proposed to solve these problems, as shown in FIG. 2 (Prior Art). The improvement in this new cell structure is that the control gate 12 includes an extended control gate portion 12a, which is located over the channel portion 8a near the source region 5. In addition, the oxide layers 7a and 7b are located between the channel portion 8b and the floating gate 10 and between the channel portion 8a and the extended control gate portion 12a, respectively. If the over-erase problem occurs, the extended control gate portion 12a can serve as a controlled switch to isolate the memory cell from the external column bias circuitry. Therefore, the current leakage can be avoided. However, the double-poly split-gate still has a drawback. Referring to FIG. 2, additional space occupied by the extended control gate 12a is required in addition to the space occupied by the floating gate 10 in the conventional memory cell. Therefore, such a memory cell structure occupies a larger chip size.
As described above, the stacked gate double-poly memory cell and the double-poly split-gate memory cell each have their own drawbacks. U.S. Pat. No. 5,856,943 discloses a modified flash memory cell, which overcomes the over-erase issue but does not increase the occupied chip size. Such a modified flash memory cell is called the triple-poly split-gate memory cell, as shown in FIG. 3. The main difference between this cell structure and the conventional two cell structures is in the gate structure. The gate structure comprises three portions, including control gate 24, floating gate 22 and select gate 20. Referring to FIG. 3, there is a large change in the placement of floating gate 22. The select gate 20 is located over the channel portion 8b near the drain region 3 and isolated from the channel portion 8b by the oxide layer 7a. Floating gate 22 extends from the upper of the select gate 20 to the channel portion 8a near the source region 5 and is isolated from the channel portion 8a by the oxide layer 7b. The control gate 24 is stacked over the floating gate 22 and the dielectric layer 26 is sandwiched between them. Therefore, the select gate 20 and the floating gate 22 are located over the channel between the drain region 3 and the source region 5.
The select gate 20 has the same function as the extended control gate 12a in solving the over-erase problem. That is, the select gate 20 can serve as a controlled switch to isolate the memory cell from the external column bias circuitry for preventing current leakage while the over-erase condition is occurring. On the other hand, the triple-poly split-gate memory cell occupies less chip space, although it also has an extended portion like the memory cell shown in FIG. 2. In the double-poly split-gate memory cell shown in FIG. 2, the chip space occupied by the floating gate 10 and the control gate 12 is almost the same as that in FIG. 1 to maintain the coupling ratio of the control gate 12 and the floating gate 10. Therefore, the extended control gate 12a is a primary factor in increasing the occupied chip space. However, in the triple-poly split-gate memory cell shown in FIG. 3, there is no limitation on the chip space occupied by the select gate 20. In addition, since the floating gate 22 and the control gate 24 are heaped over the select gate 20, a large coupling ratio between the floating gate 22 and the control gate 24 can be obtained in the less occupied chip space. Therefore, the occupied chip space of the whole gate structure is almost the same as that of the conventional stacked gate double-poly memory cell. Accordingly, such memory cell structure can effectively solve the over-erase problem without increasing the occupied chip space.
The triple-poly split-gate memory cell can be programmed by source-side hot-electron injection. While programming such a flash memory cell, a large positive voltage is applied to the control gate 24 and coupled to the floating gate 22. Therefore, an electric field can be generated between the floating gate 22 and the source 5 due to the potential difference and provides the hot electrons with sufficient energy to inject into the floating gate 22. In addition, the triple-poly split-gate memory cell can be erased by F-N tunneling effect through the drain region 3. However, such programming/erasing procedures still have several weaknesses, such as uniform injection and the electron injection efficiency.